In many types of electrical systems it is desirable to generate clock signals with various frequency and phase relationships synthesized from certain reference signals. A common way to synthesize derivatives of a reference signal is based upon the analog phase locked loop (PLL) frequency converter. Accordingly, FIG. 1 shows a traditional analog PLL 100 that takes a digital source frequency SCLK as an input to a source divider 104 that divides SCLK by an integer value S to create reference frequency fREF. A negative feedback PLL control loop 105 is formed by a phase detector 106, a charge pump 108, a low pass loop filter 110, a voltage controlled oscillator (VCO) 112, and a feedback divider 114. Phase detector 106 performs a phase difference operation on fREF and feedback frequency fBACK. That is, phase detector 106 generates a phase error signal UERR that is zero when fREF and fBACK are equal, and varies inversely with their difference. The feed-forward path 107 of the PLL control loop generates an output, or destination, frequency DCLK from VCO 112 whose output frequency is controlled by UERR through a voltage created by charge pump 108 and low pass filter 110. Specifically, charge pump 108 converts UERR to a voltage signal that is smoothed by low pass loop filter 110, thereby providing a control voltage to VCO 112. The feedback path 113 of the PLL control loop feeds frequency output DCLK into feedback divider 114 which creates the fBACK signal by dividing DCLK by an integer value F. The output frequency of DCLK is a multiple or fraction of source frequency SCLK as determined by the ratio
      F    S    .
PLL phase jitter, loop stability and response time are principally determined by the analog charge pump 108 and low pass loop filter 110 components. Capacitive elements in these analog PLL components introduce significant loop time constants and phase jitter that result in loop behavior that is difficult to understand, and predict, especially when the source frequency SCLK rapidly changes. One reason for this uncertainty, for example, is that capacitors are subject to thermal variation of their electrical characteristics. Moreover, practical implementations of analog PLL based frequency converters are often limited to a small compare period (i.e., a small values of F and S) because a large compare period requires a larger capacitor in filter 110, which is impossible in many applications. For at least these reasons, analog PLLs are very difficult to practically use for accurate frequency conversion, especially when the source frequency SCLK is not a constant value. In many types of systems, a digitally controlled generator of DCLK is required, instead of a fixed-frequency analog oscillator, for example. One conventional and important component of the generator is called a discrete-time oscillator (DTO), and is shown by way of example in FIG. 2 as DTO 200. The DTO 200 includes an n-bit adder 202 that adds a n-bit increment value SF (scale factor) to the previous output value of register 204, whereby the output value of register 204 is updated with the newly incremented value upon the next rising edge of a reference clock signal RCLK, thereby generating, over some number of RCLK cycles the n-bit staircase output represented by signal 206 The duration of each step in the staircase output signal 206 is equal to the RCLK period TRCLK. After each period of the DTO output signal 206, a carry bit 208 is generated. Carry bit 208 represents the integer part of the DTO output periods, and the staircase DTO output signal 206 contains information about the fractional part of each period. The DTO oscillation period is determined by the MODULO of the DTO adder, the value of SF, and the RCLK frequency FRCLK according to the following Equation (1):
                              F          DCLK                =                              SF            MODULO                    ×                      F            RCLK                                              (        1        )            
where SF is the n-bit scaling factor that linearly determines the output frequency of the DTO. Typically, the RCLK frequency and the MODULO are fixed, and the desired DTO output frequency is dynamically controlled by the value of SF. The value of MODULO usually equals 2n, where n is number of DTO adder bits.
The staircase DTO output signal has to be converted to DCLK signal by some output module. Thus, the first function of the output module is to create rectangular waveform of DCLK. The second function is to reduce the jitter of the DTO output period to be equal to TRCLK. A known example of an output module is illustrated by way of the block diagram in FIG. 3. In the diagram, an n-bit value SF sets the frequency of the n-bit DTO signal FDTO, which is fed into a form module 307 of an output module 305 for signal conditioning. Form module 307 generates an arbitrary wave form with the same period as FDTO by taking the output of DTO 304 as a memory address for lookup table (LUT) 308 which inputs the appropriate values from each corresponding LUT address location into digital-to-analog converter (DAC) 310, which thereby generates the desired waveform that is smoothed by low-pass filter 312. The LUT and filter are usually included to reduce harmonic frequency distortion in the DTO frequency by blocking the highest harmonic frequencies and permitting principally the main clock frequency to pass through, thereby also reducing, but not eliminating, phase jitter. Schmidt trigger 314 converts the analog representation of FDTO into a binary frequency DTO_CLK that is fed into PLL 316 for frequency conversion. Alternatively, DTO_CLK may be used as the DCLK output without PLL 316 in some applications. Another useful component in the frequency conversion of discrete signals is a direct digital synthesizer (DDS), shown by way of example in FIG. 4a. The DDS usually performs a frequency step-down function. Summation unit 402 adds the n-bit value SF stored in SF register 404 to the n-bit value from the output of phase accumulator 406. The sum is synchronously updated upon each rising edge of SCLK. Phase accumulator 406 feeds the n-bit DDS frequency FDDS to the output module, and feeds back FDDS to summation unit 402, thereby generating, over some number of SCLK cycles, a staircase periodic signal 408 with a frequency given by the formula in Equation (2) below:
                              F          DDS                =                              SF                          2              n                                ⁢                      F            SCLK                                              (        2        )            
where FSCLK is the frequency value of SCLK. Output module 410 converts the DDS frequency signal FDDS to a destination clock DCLK. Output module 410 could, for example, convert the staircase waveform into a binary clock signal with frequency FDDS. It should be noted that the jitter in the period of staircase periodic signal 408 is equal to the SCLK period. If the SCLK period varies over a wide range (i.e., has high jitter), then it may be difficult (or impossible) to design the output module to reduce the jitter effectively.
Another kind of relevant DDS frequency converter 450 is illustrated by way of example in FIG. 4b. Source divider 452 divides SCLK by an integer value SDIV to create reference signal REF. Destination divider 464 divides DCLK by and integer value DDIV generate a Feedback signal. Phase detector 454 compares the positions of the REF and Feedback signals to each compare period where the compare period is the time between two consequent REF signals. The Freq_set output values of the phase detector are generally proportional to the difference between compare period and feedback period. Frequency value generator 456 accumulates the Freq_set values from phase detector 454 and creates the output value Freq_val that is fed as an input to DTO 457. DTO 457 consists of adder 458 and register 460. The DTO output is then conditioned by output module 462 to produce the DCLK frequency.
Important areas where frequency converters are often used include computer CRT and LCD monitors. In such devices, the output clock period TDCLK and input clock period TSCLK follow the Equation (3) below:ShTOTAL×SvTOTAL×TSCLK=DhTOTAL×DvTOTAL×TDCLK  (3)
Where
ShTOTAL is the number of SCLK periods in the source line; SvTOTAL is the number of lines in the source frame;
DhTOTAL is the number of DCLK periods in the destination line; DvTOTAL is the number of lines in the destination frame;
TSCLK is the duration of the source clock period; and
TDCLK is the duration of the destination clock period.
Frequency converters in devices where frame rate conversion is used, generally follow Equation (4) below:m×ShTOTAL×SvTOTAL×TSCLK=n×DhTOTAL×DvTOTAL×TDCLK  (4)
Where m, n are integers.
The maximum value of SDIV required in frequency converter 450 is equal to m×ShTOTAL×SvTOTAL, and the compare period is m source frames. The SDIV and compare period can be reduced if values m×ShTOTAL×SvTOTAL and n×DhTOTAL×DvTOTAL have common denominator. In some cases, however, it is impossible to have large common denominator. If there is a step change in the SCLK period, TSCLK, then the DCLK period, TDCLK, in frequency converter 450 gradually will converge to a new stable state. The time it takes to converge (i.e., response time) depends on the compare period. The longer the compare period, the more time it will take frequency converter 450 to converge, which can be up to several frames. However, in many CRT/LCD monitor applications a long response time is not acceptable.
Phase detector 454 has to correctly resolve a wide range of situations. One such situation, for example, is when TDCLK is greater than two times more or less than TSCLK. As can be appreciated, phase detector 454 performs both logical and calculation operations, and is, therefor, generally difficult to design.
Although frequency converters generally work well in many cases, there is a continual need for improved digital frequency converters designs. In particular, there is a general need for frequency converters that have a fast response time, and simple phase error detection mechanism. It would be desirable for these frequency converters to work well in CRT/LCD monitors applications as well.